Semiconductor device with improved signal transmission characteristics

ABSTRACT

The semiconductor device includes a solder ball connected to a pad, and located below the pad, a first wiring electrically connected to the pad, and located above the pad, and a second wiring electrically connected to the first wiring. At this time, a width of the first wiring is greater than a width of the second wiring. Accordingly, high-frequency noise can be reduced while improving signal transmission characteristics.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2019-007125 filed onJan. 18, 2019 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device, for example,the present invention relates to a technique which can be applied to asemiconductor device including a wire substrate.

Japanese Unexamined Patent Application No. 2014-82298 describes atechnique for realizing good signal transmission characteristics over awide band.

SUMMARY

For example, in a semiconductor device which performs high-speed signaltransmission typified by 56 Gbps, improvement of signal transmissioncharacteristics is desired. However, the improvement of the signaltransmission characteristics means that not only a signal but also ahigh-frequency noise (noise having a frequency higher than the Nyquistfrequency) is often taken into the semiconductor device. Therefore, atechnique capable of reducing high-frequency noise while improvingsignal transmission characteristics is desired.

Other objects and novel features will become apparent from thedescription of this specification and the accompanying drawings.

The semiconductor device in one embodiment includes an externalconnection terminal connected to a pad, and located below the pad, afirst wiring electrically connected to the pad, and located above thepad, and a second wiring electrically connected to the first wiring. Atthis time, a width of the first wiring is greater than a width of thesecond wiring.

According to one embodiment, high-frequency noise can be reduced whileimproving signal transmission characteristics.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a schematic configuration of a transmissionsystem.

FIG. 2 is a plan view showing a schematic configuration of asemiconductor device.

FIG. 3 is a cross-sectional view schematically showing a cross sectionof a semiconductor device.

FIG. 4 is a diagram schematically showing a characteristic impedance atthe connecting portion between the semiconductor device and the mountingsubstrate.

FIG. 5 is a schematic diagram showing the configuration of a specificlow impedance delay portion.

FIG. 6 is a diagram schematically showing a characteristic impedance atthe connecting portion between the semiconductor device and the mountingsubstrate in the first related art.

FIG. 7 is a schematic diagram showing a specific configuration of a lowimpedance delay portion and a high impedance delay portion in the firstrelated art.

FIG. 8 is a diagram for explaining that reflection loss increases in ahigh-frequency signal.

FIG. 9 is a diagram illustrating a second related technique.

FIG. 10 is a diagram schematically showing a characteristic impedance atthe connecting portion between the semiconductor device and the mountingsubstrate in the countermeasure proposal.

FIG. 11 is a diagram for explaining a specific configuration of thecountermeasure proposal.

FIG. 12 is an equivalent circuit diagram of a connection portion betweena semiconductor device and a mounting substrate.

FIG. 13 is a diagram for explaining the basic idea in presentembodiment.

FIG. 14 is a diagram for explaining that the signal transmissioncharacteristic can be improved.

FIG. 15 is a graph showing the relationship between frequency andreflection loss.

FIG. 16 is a diagram for explaining that high-frequency noise can bereduced.

FIG. 17 is a graph showing the relationship between frequency andreflection loss.

FIG. 18 is a graph schematically showing a band-limiting filter realizedby the basic idea in the embodiment.

FIG. 19 is a diagram for explaining the basic idea in the presentembodiment.

FIG. 20 is a diagram schematically showing the connecting parts betweenthe mounting substrate and the semiconductor device.

FIG. 21 is a cross-sectional view cut along line A-A of FIG. 20.

FIG. 22A shows a layout pattern of the first wiring layer.

FIG. 22B shows a layout pattern of the second wiring layer.

FIG. 22C shows a layout pattern of the third wiring layer.

FIG. 22D shows a layout pattern of the fourth wiring layer.

FIG. 23 is a graph showing the result of comparing the connectionstructure of the countermeasure shown in FIG. 11 with the connectionstructure in the present embodiment shown in FIG. 20 with respect to thefrequency dependence of the reflection loss and the frequency dependenceof the insertion loss.

FIG. 24 is a diagram showing the connecting parts between the mountingsubstrate and the semiconductor device in the present first modifiedexample.

FIG. 25 is a cross-sectional view cut along line A-A of FIG. 24.

FIG. 26A shows a layout pattern of the first wiring layer.

FIG. 26B shows a layout pattern of the second wiring layer, and 26Cshows a layout pattern of the third wiring layer.

FIG. 27 is a graph showing the result of comparing the connectionstructure of the countermeasure shown in FIG. 11 and the connectionstructure in the present first modified example shown in FIG. 24 withrespect to the frequency dependence of the reflection loss and thefrequency dependence of the insertion loss.

FIG. 28A is a graph showing the frequency dependence of the height ofthe eye pattern.

FIG. 28B is a graph showing the frequency dependence of the width of theeye pattern.

FIG. 29A shows the eye pattern in the countermeasure plan when there isno high-frequency noise.

FIG. 29B shows the eye pattern in first modified example when there isno high-frequency noise.

FIG. 30A shows the eye pattern in the countermeasure plan when there ishigh-frequency noise.

FIG. 30B shows the eye pattern in first modified example when there ishigh-frequency noise.

FIG. 31A is a graph showing the frequency dependence of the height ofthe eye pattern.

FIG. 31B is a graph showing the frequency dependence of the width of theeye pattern.

FIG. 32A shows the eye pattern in the countermeasure plan when there isno high-frequency noise.

FIG. 32B shows the eye pattern in first modified example when there isno high-frequency noise.

FIG. 33A shows the eye pattern in the countermeasure plan when there ishigh-frequency noise.

FIG. 33B shows the eye pattern in first modified example when there ishigh-frequency noise.

FIG. 34A is a graph showing the frequency dependence of the height ofthe eye pattern.

FIG. 34B is a graph showing the frequency dependence of the width of theeye pattern.

FIG. 35A shows the eye pattern in the countermeasure plan when there isno high-frequency noise.

FIG. 35B shows the eye pattern in first modified example when there isno high-frequency noise.

FIG. 36A shows the eye pattern in the countermeasure plan when there ishigh-frequency noise.

FIG. 36B shows the eye pattern in first modified example when there ishigh-frequency noise.

FIG. 37 is a schematic diagram showing the connecting structures in thethird modified example.

FIG. 38 is a schematic diagram showing the connecting structures in thefourth modified example.

FIG. 39 is a schematic diagram showing the connecting structures in thefourth modified example.

FIG. 40 is a graph showing the frequency dependence of reflection lossand insertion loss.

FIG. 41 is a graph showing the frequency dependence of reflection lossand insertion loss.

DETAILED DESCRIPTION

In the following embodiments, when required for convenience, thedescription will be made by dividing into a plurality of sections orembodiments, but except when specifically stated, they are notindependent of each other, and one is related to the modified example,detail, supplementary description, or the like of part or all of theother.

In the following embodiments, the number of elements, etc. (includingthe number of elements, numerical values, quantities, ranges, etc.) isnot limited to the specific number, but may be not less than or equal tothe specific number, except for cases where the number is specificallyindicated and is clearly limited to the specific number in principle.

Furthermore, in the following embodiments, it is needless to say thatthe constituent elements (including element steps and the like) are notnecessarily essential except in the case where they are specificallyspecified and the case where they are considered to be obviouslyessential in principle.

Similarly, in the following embodiments, when referring to the shapes,positional relationships, and the like of components and the like, it isassumed that the shapes and the like are substantially approximate to orsimilar to the shapes and the like, except for the case in which theyare specifically specified and the case in which they are considered tobe obvious in principle, and the like. The same applies to the abovenumerical values and ranges.

In all the drawings for explaining the embodiments, the same members aredenoted by the same reference numerals in principle, and repetitivedescriptions thereof are omitted. Note that even plan view may behatched for the sake of clarity.

Schematic Configuration of Transmission System

FIG. 1 is a diagram showing a schematic configuration of transmissionsystem.

In FIG. 1, a transmission system is provided with a transmission unit TXfor transmitting a signal and a reception unit RX for receiving thesignal, and the transmission unit TX and the reception unit RX areconnected by a transmission line.

As shown in FIG. 1, the receiving unit RX is incorporated in asemiconductor device SA, and the semiconductor device SA is mounted on amounting substrate MB, for example. On the other hand, the transmittingunit TX is incorporated in an external device provided outside themounting substrate MB, for example.

The transmitting unit TX and the receiving unit RX are electricallyconnected to each other by, for example, differential wirings composedof a transmission line TL1 and a transmission line TL2.

Structure of Semiconductor Device

FIG. 2 is a plan view showing a schematic configuration of thesemiconductor device.

In FIG. 2, the semiconductor device SA has, for example, a wiringsubstrate WB having a rectangular planar shape, and the semiconductorchip CHP is mounted on the wiring substrate WB. In the semiconductorchip CHP, an integrated circuit constituting a receiving section isformed. The receiving section formed in the semiconductor chip CHP iselectrically connected to the transmission line formed in the wiringsubstrate WB.

FIG. 3 is a cross-sectional view schematically showing a cross sectionof a semiconductor device;

In FIG. 3, the semiconductor device SA is mounted on the mountingsubstrate MB. The semiconductor device SA has a wiring substrate WB anda semiconductor chip CHP flip-chip connected to the surface of thewiring substrate WB. And, the semiconductor chip CHP is electricallyconnected to a multi-layer wiring formed inside the wiring substrate WB.The multi-layer wiring formed inside the wiring substrate WB iselectrically connected to a pad PD formed on the back surface of thewiring substrate WB. And, the pad PD is electrically connected to asolder ball (external connection terminal) SB mounted on the pad PD. Thewiring substrate WB comprising the semiconductor device SA is connectedwith the wiring (transmission line) formed in the mounting substrate MBby way of the solder ball SB. In the semiconductor device SA configuredas described above, signals propagating through the wiring (transmissionline) formed on the mounting substrate MB are transmitted through themulti-layer wiring formed inside the wiring substrate WB via the pads PDmounting the solder balls SB, and then received by the receiving unit ofthe semiconductor chip CHP flip-chip connected to the wiring substrateWB.

FIG. 4 is a diagram schematically showing a characteristic impedance atthe connecting portion between the semiconductor device and the mountingsubstrate. In FIG. 4, the characteristic impedance of the wiring 100formed in the wiring substrate is 50Ω. Similarly, the characteristicimpedance of the wires 200 formed in the mounting substrate is also 50Ω.Here, the wiring substrate and the mounting substrate are connected by asolder ball mounted on a pad, and a connecting portion including the padand the solder ball becomes a low impedance delay portion 10 having acharacteristic impedance smaller than 50Ω. This is because, for example,if the resistor is negligible and the inductance is “L” and thecapacitance is “C”, the characteristic impedance of the transmissionline is expressed by √(L/C). That is, the area of the connection portionincluding the pad and the solder ball is larger than that of the wiring100 of the wiring substrate constituting the transmission line or thewiring 200 of the mounting substrate, and the fact that the area islarger means that the capacitance “C” is larger, and as a result, thecharacteristic impedance of the connection portion including the pad andthe solder ball is smaller than 50Ω. Therefore, the connection portionincluding the pad and the solder ball constitutes the low impedancedelay portion 10.

As a result, as shown in FIG. 4, a characteristic impedance mismatchoccurs between the wiring 100 and the low impedance delay portion 10 andbetween the low impedance delay portion 10 and the wiring 200. At theboundary where the characteristic impedance mismatch occurs, thereflection loss of the signal becomes large. As a result, the signaltransmission performance is deteriorated.

FIG. 5 is a schematic diagram showing a specific configuration of thelow impedance delay portion 10.

In FIG. 5, the low impedance delay portion 10 includes a pad PD and asolder ball SB. At this time, the wiring 100 formed in the wiringsubstrate is electrically connected to the pad PD, and the wiring 200formed in the mounting substrate is electrically connected to the solderball SB. As shown in FIG. 5, since the effective width of the pad PD andthe solder ball SB is larger than, for example, the width of the wiring100 constituting the transmission line having the characteristicimpedance of 50Ω, it is understood that the connection portion includingthe pad PD and the solder ball SB becomes the low impedance delayportion 10 having the characteristic impedance smaller than 50Ω.

Therefore, in order to reduce the reflection loss of the signal causedby the mismatch of the characteristic impedance between the transmissionline and the low impedance delay portion 10, there is a first relatedtechnique described below.

Description of First Related Art

The “related art” referred to in the present specification is atechnology having a problem newly found by the inventor, and is not aknown prior art, but is a technology described with the intention of aprerequisite technology (unknown technology) of a new technical idea,although it is not a known prior art.

FIG. 6 is a diagram schematically showing a characteristic impedance atthe connecting portion between the semiconductor device and the mountingsubstrate in the first related art. In the first related art shown inFIG. 6, a high impedance delay portion 20 having a characteristicimpedance larger than 50Ω is provided between the wiring 100 and the lowimpedance delay portion 10. At this time, in the first related art, thecharacteristic impedance of the high impedance delay portion 20 isadjusted so that the characteristic impedance becomes 50Ω by combiningthe high impedance delay portion 20 and the low impedance delay portion10. As a result, for example, the combination of the low-impedance delayunit 10 and the high-impedance delay unit 20 appears to be equivalent tothe combination of the 50Ω transmission line for the signal propagatingthrough the wire 200 of the mounting substrate, and the combination ofthe low-impedance delay unit 10 and the high-impedance delay unit 20appears to be equivalent to the combination of the 50Ω transmission linefor the signal propagating through the wire 200. As a result, signalsthat have propagated through the wiring 200 of the mounting substrateare smoothly propagated to the wiring 100 of the wiring substratewithout substantially causing reflectance losses. That is, in the firstrelated art, the influence of the low impedance delay portion having asmall characteristic impedance is offset by the influence of the highimpedance delay portion having a large characteristic impedance, therebyreducing the reflection loss caused by the discontinuity of thecharacteristic impedance.

FIG. 7 is a schematic diagram showing a specific configuration of a lowimpedance delay portion and a high impedance delay portion in the firstrelated art.

In FIG. 7, the low impedance delay portion 10 is configured to include apad PD and a solder ball SB, while the high impedance delay portion 20is configured to include a wiring WL. As described above, the highimpedance delay portion 20 having the characteristic impedance largerthan 50Ω is realized by using the parasitic inductance due to the wiringWL.

In the first related art, the reflection loss of the signal can bereduced by providing the high impedance delay portion 20 that cancelsthe influence of the low impedance delay portion 10.

However, when the frequency of the propagating signal increases, themeasures in the first related art described above become insufficient.This point will be described below.

FIG. 8 is a diagram for explaining that reflection loss increases in ahigh-frequency signal.

In FIG. 8, when the frequency of the signal is low, for example, thecombination of the low impedance delay portion 10 and the high impedancedelay portion 20 appears to be equivalent to the combination of the 50Ωtransmission line for the signal propagating through the wire 200 of themounting substrate. On the other hand, when the frequency of the signalbecomes higher, the low impedance delay portion 10 and the highimpedance delay portion 20 appear to be separate from each other, notthe mean of the low impedance delay portion 10 and the high impedancedelay portion 20, for the signal propagating through the wire 200 of themounting substrate. This means that the discontinuous region of thecharacteristic impedance appears to be increased for the high-frequencysignal. That is, when the above-described first related technique isapplied to a high-frequency signal, for example, as shown in FIG. 8, itappears that a discontinuous region of characteristic impedance existsat the boundary between the wiring 200 and the low-impedance delay unit10, the boundary between the low-impedance delay unit 10 and thehigh-impedance delay unit 20, and the boundary between thehigh-impedance delay unit 20 and the wiring 100.

As a result, as shown in FIG. 8, in the first related art, thereflection loss with respect to the high-frequency signal becomes large.In this regard, in order to reduce reflection loss with respect to ahigh-frequency signal, there is a second related art described below.

Description of Second Related Art

FIG. 9 is a diagram for explaining the second related art.

In FIG. 9, the low impedance delay portion 10 is configured to include apad PD and a solder ball SB, while the high impedance delay portion 20is configured to include a wiring WL. This configuration is the same asthat of the first related art shown in FIG. 7. Further, in the secondrelated art, as shown in FIG. 9, an electromagnetic wave absorber EMA isprovided above the pad PD. As a result, according to the second relatedart, even in the high-frequency signal, a part of the electromagneticwave scattered in the discontinuous region of the characteristicimpedance is absorbed. As a result, according to the second related art,the reflection loss for the high-frequency signal can be reduced.

Consideration of Improvement to Second Related Art

However, the inventors of the present invention have investigated andnewly found that in the second related art, since the discontinuity inthe discontinuous region of the characteristic impedance is too large,too many electromagnetic waves are scattered in the discontinuous regionof the characteristic impedance, and the electromagnetic wave absorberEMA cannot completely absorb the electromagnetic waves. That is, in thesecond related art, there is room for improvement from the viewpoint ofsufficiently reducing the reflection loss with respect to thehigh-frequency signal. In particular, the signal transmissioncharacteristics are deteriorated with respect to a high-frequency signalhaving a frequency of 25 GHz or more. Therefore, the second related artis insufficient from the viewpoint of ensuring signal transmissioncharacteristics with respect to a high-frequency signal used for signaltransmission of, for example, 56 Gbps or more. Therefore, the presentinventor has devised a room for improvement existing in the secondrelated art. Draft measures of the first embodiment to which the presentinvention is applied will be described.

Proposed Measures

FIG. 10 is a diagram schematically showing a characteristic impedance atthe connecting portion between the semiconductor device and the mountingsubstrate in the countermeasure proposal. In the measure plan shown inFIG. 10, the discontinuity of the characteristic impedance in the lowimpedance delay portion 10 and the discontinuity of the characteristicimpedance in the high impedance delay portion 20 are reduced. In thiscase, considering that the smaller the discontinuity of thecharacteristic impedance, the smaller the scattering of thehigh-frequency signal (electromagnetic wave) in the discontinuous regionof the characteristic impedance, the countermeasure shown in FIG. 10reduces the scattering of the electromagnetic wave in the discontinuousregion of the characteristic impedance as compared with the secondrelated art shown in FIG. 8. As a result, in the countermeasureproposal, the electromagnetic wave absorber can sufficiently absorb theelectromagnetic wave scattered in the discontinuous region of thecharacteristic impedance by providing the electromagnetic wave absorber.This means that the reflection loss for the high-frequency signal can besufficiently reduced according to the countermeasure proposal. As aresult, according to the countermeasure proposal, it is possible toreduce a transmission loss (insertion loss) in a high-frequency signal.

FIG. 11 is a diagram for explaining a specific configuration of thecountermeasure proposal.

In FIG. 11, in the countermeasure plan, the length of the wiring WLconstituting the high impedance delay portion 20 is short and thick.Thus, the parasitic inductance of the wiring WL can be reduced.Therefore, as shown in FIG. 10, the discontinuity of the high impedancedelay portion 20 formed of the wiring WL is alleviated. On the otherhand, in FIG. 11, in the countermeasure plan, the size of the pad PD andthe size of the solder ball included in the low impedance delay portion10 are reduced. As a result, the parasitic capacitance of the lowimpedance delay portion 10 can be reduced. Therefore, as shown in FIG.10, the discontinuity of the low impedance delay portion 10 includingthe pad PD and the solder ball SB is alleviated.

As described above, in the countermeasure plan, the deviation(discontinuity) of the characteristic impedance in the low impedancedelay portion 10 from 50Ω and the deviation (discontinuity) of thecharacteristic impedance in the high impedance delay portion 20 from 50Ωcan be reduced. Thereby, according to the countermeasure proposalincluding the electromagnetic wave absorber EMA, the electromagneticwave scattered in the discontinuous region of the characteristicimpedance can be sufficiently absorbed by the electromagnetic waveabsorber EMA, and consequently, according to the countermeasureproposal, the reflection loss with respect to the high-frequency signalcan be sufficiently reduced. Therefore, according to the countermeasureproposal, it is possible to reduce the transmission loss (insertionloss) in the high-frequency signal.

Knowledge Found by Inventor

As described above, the countermeasure proposal is useful in that thetransmission loss in the high-frequency signal can also be reduced, sothat the signal transmission band can be improved. However, the factthat the signal transmission band can be improved means thathigh-frequency noise can also pass through well. That is, in thecountermeasure proposal, the high-frequency signal and thehigh-frequency noise are passed through well. Therefore, in thecountermeasure proposal, while the signal transmission characteristiccan be improved, the high-frequency noise is also passed well, so thatthe deterioration of the high-frequency noise tolerance becomes obviousas a problem. Particularly, in the countermeasure proposal, when amulti-level modulated signal vulnerable to noise is transmitted, thetolerance to high-frequency noise (noise having a frequency componenthigher than the Nyquist frequency) is deteriorated.

In this regard, high frequency noises are generated by crosstalk, signalreflections, and the like on the mounting substrate and enter thesemiconductor device mounted on the mounting substrate. Therefore, whenadopting a countermeasure for passing high-frequency noise well togetherwith a high-frequency signal, it is necessary to use a filter forpassing the high-frequency signal while removing the high-frequencynoise. However, the addition of such a filter increases the system cost.Also, due to the high frequency of the signal (e.g., 56 Gbps) per se,filters that pass high frequency signals while removing high frequencynoises are difficult to obtain, fabricate, and even mount on a mountingsubstrate, regardless of costs.

Therefore, present embodiment has devised the above-mentionedcountermeasure proposal. Hereinafter, the technical idea in the presentembodiment to which the present invention is applied will be described.

Basic Concept in Present Embodiment

FIG. 12 is a diagram showing an equivalent circuit diagram of aconnection portion between the semiconductor device and the mountingsubstrate.

In FIG. 12, a wiring 200 is a wiring formed in a mounting substrate. Onthe other hand, the wiring 100 is a wiring formed in a semiconductordevice mounted on a mounting substrate. A connection portion between thesemiconductor device and the mounting substrate is provided between thewiring 200 and the wiring 100, and this connection portion is composedof a low impedance delay portion 10 and a high impedance delay portion20. Each of the low impedance delay portion 10 and the high impedancedelay portion 20 is composed of an L/C circuit. The low impedance delayportion 10 and the high impedance delay portion 20 are respectivelyconfigured by the value of the inductance and the value of thecapacitance of the L/C circuit.

FIG. 13 is a diagram for explaining the basic idea in the presentembodiment.

FIG. 13 schematically shows a characteristic impedance at the connectingportion between the semiconductor device and the mounting substrate inthe present embodiment.

In present embodiment, in particular, it is assumed that high-frequencysignals propagate from the wiring 200 formed in the mounting substrateto the wiring 100 formed in the semiconductor device, and as shown inFIG. 13, a boundary region between the wiring 200 and the low-impedancedelay portion 10 of the connection portion is used as an input end, anda boundary region between the wiring 100 and the high-impedance delayportion 20 of the connection portion is used as an output end.

At this time, the characteristic impedance of the wiring 200 and thecharacteristic impedance of the wiring 100 are both 50Ω. On the otherhand, the characteristic impedance of the low impedance delay portion 10is smaller than 50Ω, and the characteristic impedance of the highimpedance delay portion 20 is larger than 50Ω.

Therefore, in present embodiment, a discontinuity in the characteristicimpedance occurs at the input end, which is the interface between thewire 200 and the low impedance delay portion 10. Similarly, in presentembodiment, a discontinuity in the characteristic impedance occurs alsoin the interface area between the low impedance delay portion 10 and thehigh impedance delay portion 20. Further, in the present embodiment, adiscontinuity in the characteristic impedance also occurs at the outputend, which is the interface area between the high impedance delayportion 20 and the wire 100.

Therefore, the high-frequency signal propagating through the wiring 200is subjected to multiple reflection due to discontinuity of thecharacteristic impedance existing in the connection portion between theinput end and the output end, i.e., the low-impedance delay portion 10and the high-impedance delay portion 20, thereby causing reflectionloss. At this time, the reflection loss of the high-frequency signal canbe reduced by performing the phase adjustment between the input end andthe output end. Specifically, the phase of the high-frequency signalincident on the input end and the phase of the reflection signalreflected at the output end and returned to the input end again afterincident from the input end are adjusted so as to be shifted by 180degrees, whereby the reflection loss of the high-frequency signal at theinput end and the output end can be reduced. This is because thereflection signal returning to the wiring 200 is reduced when the phaseof the high-frequency signal incident on the input end and the phase ofthe reflection signal returning to the input end again after beingincident from the input end are shifted by 180 degrees.

As described above, in the present embodiment, first, the phase of thehigh-frequency signal incident on the input end and the phase of thereflection signal incident on the input end and then reflected on theoutput end and returned to the input end are adjusted so as to be 180degrees. That is, as shown in FIG. 14, when the phase adjustment isperformed at the connection portions (the low impedance delay portion 10and the high impedance delay portion 20), the reflected waves at theinput end and the output end are reduced. This means that an impedancepole is formed, whereby the signal transmission characteristics can beimproved. This will be explained using FIG. 15.

FIG. 15 is a graph showing the relationship between frequency andreflection loss.

In FIG. 15, when the phase of the high-frequency signal incident on theinput end and the phase of the reflection signal reflected at the outputend and returned to the input end again after incident from the inputend are adjusted to be 180 degrees, reflection loss is remarkablyreduced at the frequency causing the phase shift of 180 degrees, and asa result, an impedance pole is formed. At this time, when the firstfrequency shown in FIG. 15 is a Nyquist frequency, the reflection lossof the first frequency signal can be reduced by providing an impedancepole. As a result, the transmission loss (insertion loss) of the firstfrequency signal can be reduced, so that the signal transmissioncharacteristic can be improved.

However, as shown in FIG. 15, when the phase adjustment is performed toform the impedance pole, not only the Nyquist frequency but also thereflection loss of the second frequency signal higher than the Nyquistfrequency is reduced. For example, when the second frequency is afrequency of the high-frequency noise, the transmission loss of thehigh-frequency noise is also reduced when the phase adjustment isperformed.

First, in order to reduce transmission losses of the first frequencysignal (signal of Nyquist frequency), the present embodimentintentionally shifts the characteristic impedance of the connectionportion seen from the input end (or the characteristic impedance of theconnection portion seen from the output end) from 50Ω on the assumptionthat the phase between the input end and the output end is adjusted.Thus, according to the present embodiment, it is possible to reduce thehigh-frequency noise (noise of the second frequency higher than theNyquist frequency) while improving the signal transmissioncharacteristics of the first frequency signal (signal of the Nyquistfrequency).

That is, as shown in FIG. 16, intentionally shifting the characteristicimpedance of the connection portion as viewed from the input end (or thecharacteristic impedance of the connection portion as viewed from theoutput end) from 50Ω means that the impedance pole does not appearclearly, thereby increasing the reflection loss in the frequency bandhigher than the impedance pole. As a result, according to the presentembodiment, it is possible to realize reduction of high-frequencynoises.

This will be explained using FIG. 17.

FIG. 17 is a graph showing the relationship between frequency andreflection loss.

In FIG. 17, the dotted line is a graph showing the frequency dependenceof the reflection loss when the characteristic impedance of theconnection portion (the combination of the low impedance delay portion10 and the high impedance delay portion 20) seen from the input end is50Ω. As shown by the dotted line in FIG. 17, when the phase adjustmentis performed and the characteristic impedance of the connection portion(combination of the low impedance delay portion 10 and the highimpedance delay portion 20) seen from the input end is set to 50Ω, theimpedance pole clearly appears, and as a result, the reflection loss canbe greatly reduced not only at the first frequency but also at thesecond frequency. This means that not only the signals of the Nyquistfrequency but also the transmission losses of the high-frequency noiseare reduced, which leads to a good incorporation of the high-frequencynoise from the mounting substrate into the semiconductor device,resulting in a deterioration of the high-frequency noise immunity.

On the other hand, in FIG. 17, the solid line is a graph showing thefrequency dependence of the reflection loss when the characteristicimpedance of the connection portion (the combination of the lowimpedance delay portion 10 and the high impedance delay portion 20) seenfrom the input end intentionally deviates from 50Ω. As shown by thesolid line in FIG. 17, while the phase adjustment is performed, when thecharacteristic impedance of the connection portion seen from the inputend (the combination of the low impedance delay portion 10 and the highimpedance delay portion 20) is intentionally shifted from 50Ω, theimpedance pole does not appear clearly. As a result, the reflection losscan be reduced at the first frequency lower than the impedance pole,while the reflection loss can be increased at the second frequencyhigher than the impedance pole. According to the present embodiment, itis possible to reduce high-frequency noises while improving the signaltransmission characteristics of the Nyquist frequency signal.

The basic idea in the present embodiment is a combination of the idea ofadjusting the phase of the high-frequency signal incident on the inputend and the phase of the reflection signal incident on the input end andreflected on the output end and returning to the input end so as to be180 degrees, and the idea of intentionally shifting the characteristicimpedance of the connecting portion (the combination of thelow-impedance delay portion 10 and the high-impedance delay portion 20)seen from the input end from 50Ω.

According to the basic idea of the present embodiment, it is possible toremove high-frequency noises having a higher frequency than theimpedance pole while improving the signal transmission characteristicsin a frequency band lower than the impedance pole. In other words, thebasic idea of the present embodiment is to configure the band-limitingfilters by devising a combination of the low-impedance delay unit 10 andthe high-impedance delay unit 20.

FIG. 18 is a diagram schematically showing band-limiting filtersrealized by the basic idea in the present embodiment. As shown in FIG.18, according to the band-limiting filter realized by the basic idea inthe present embodiment, it is possible to increase the transmission loss(insertion loss) of the second frequency (high-frequency noise) whileimproving the signal transmission characteristics at the first frequency(Nyquist frequency). In other words, according to the band-limitingfilter realized by the basic idea in present embodiment, it is possibleto reduce high-frequency noises while improving signal transmissioncharacteristics.

To summarize the above, as shown in FIG. 19, the basic idea in thepresent embodiment is a technical idea in which the connection partbetween the mounting substrate and the semiconductor device functions asa band-limiting filter by adjusting the phase of the connection part anddevising to shift the characteristic impedance from 50Ω on theassumption that the connection part including the low impedance delaypart 10 and the high impedance delay part 20 exists.

Hereinafter, examples of realizing the basic idea in present embodimentby devising layout patterns at the connecting portions between themounting substrate and the semiconductor device will be described. Thatis, in the following, a specific configuration will be described inwhich a layout pattern of a high-impedance delay unit provided in aconnection portion between the mounting substrate and the semiconductordevice is devised to cause the connection portion to function as aband-limiting filter.

Specific Configuration

FIG. 20 is a diagram schematically showing a connecting portion betweenthe mounting substrate and the semiconductor device.

In FIG. 20, a wiring 100 a and a wiring 100 b are wirings formed on thesemiconductor device wiring substrate, and constitute a differentialwiring. On the other hand, the wirings 200 a and 200 b are wiringsformed in the mounting substrate, and constitute differential wirings.

As shown in FIG. 20, the wiring 100 a and the wiring 200 a are connectedby a connecting portion between the mounting substrate and thesemiconductor device. Specifically, the connecting portion includes awiring WL1 connected to the wiring 100 a, a wiring WL2 connected to thewiring WL1, and pads PD1 connected to the wiring WL2. At this time, thewiring 100 a, the wiring WL1 and the wiring WL2 are signal wirings, andthe pad PD1 is a signal pad. In particular, the signal wiring can becomposed of, for example, a signal wiring for transmitting a binarydigital signal or a signal wiring for transmitting a quaternary digitalsignal.

Here, the width of the wiring WL1 is larger than the width of the wiring100 a, and the width of the wiring WL2 is larger than the width of thewiring WL1. That is, the relationship of the width of the wiring 100a<the width of the wiring WL1<the width of the wiring WL2 isestablished. For example, the width of the wiring 100 a is 23 μm, andthe width of the wiring WL1 is 60 μm. Further, the widths of the wiresWL2 are 80 micrometers.

FIG. 21 is a cross-sectional view cut along the line A-A in FIG. 20.

In FIG. 21, a wiring 200 a is formed on the surface of the mountingsubstrate MB, and a solder ball SB, which is an external connectionterminal, is mounted on the wiring 200 a. a pad PD1 is formed on thesolder ball SB. The pad PD1 is formed on the wiring substrate of thesemiconductor device, and the solder ball SB is disposed so as to besandwiched between the pad PD1 and the wiring 200 a formed on themounting substrate MB. As a result, the wiring substrate of thesemiconductor device and the mounting substrate MB are electricallyconnected to each other via the solder ball SB.

As shown in FIG. 21, four wiring layers are formed in the wiringsubstrate, and pads PD1 connected to the solder balls SB are formed inthe lowermost wiring layer L1. The planar shape of the padding PD1includes a circular shape. As shown in FIG. 21, the pads PD1 areconnected to the wirings RL formed in the wiring layer L2 above thewiring layer L1 via vias. The wiring RL formed in the wiring layer L2 isconnected to the wiring WL2 formed in the wiring layer L3 above thewiring layer L2 through a via portion. As shown in FIG. 20, theinterconnection WL2 is disposed so as to overlap with the pads PD1 inplan view. In plan view, the interconnection WL2 extends along thecircumference of the pads PD1. In particular, in FIG. 20, the wiring WL2has one end portion and the other end portion, and the angle θ1 formedby the imaginary line VL1 connecting the center point of the pad PD1 andthe one end portion of the wiring WL2 and the imaginary line VL2connecting the center point of the pad PD1 and the other end portion ofthe wiring WL2 is 180 degrees or more. In particular, the angle θ1formed by the imaginary line VL1 and the imaginary line VL2 can be setto an angle greater than or equal to 220 degrees and less than or equalto 340 degrees.

As shown in FIG. 21, the wiring WL2 formed in the wiring layer L3 isconnected to the wiring WL1 formed in the wiring layer L4 above thewiring layer L3 via a via portion. The wiring WL1 formed in the wiringlayer L4 is connected to the wiring 100 a formed in the same wiringlayer L4. In this manner, the wiring 100 a formed in the wiringsubstrate and the wiring 200 formed in the mounting substrate MB areelectrically connected to each other via the connecting portion betweenthe wiring substrate and the mounting substrate MB. At this time, inFIG. 21, for example, the low-impedance delay unit 10 shown in FIG. 12is configured by the solder balls SB and the pads PD1. On the otherhand, the interconnection WL2 constitutes, for example, thehigh-impedance delay unit 20 shown in FIG. 12.

FIGS. 22A and 22B are a plan view schematically showing a layout patternof each wiring layer constituting the multilayered wiring layer formedin the wiring substrate. In particular, FIG. 22A is a diagram showing alayout pattern of the wiring layer L1, and FIG. 22B is a diagram showinga layout pattern of the wiring layer L2. FIG. 22C is a diagram showing alayout pattern of the wiring layer L3, and FIG. 22D is a diagram showinga layout pattern of the wiring layer L4.

As shown in FIG. 22A, a pad PD1 to which a signal potential (signalvoltage) is applied is formed in the interconnection layer L1, and aground pattern GP1 to which a reference potential (ground voltage) issupplied is formed so as to surround the pad PD1 at a distance from theinterconnection layer L1. The broken line indicates the position of thesolder ball supplying the ground potential.

Next, as shown in FIG. 22B, ground patterns GP2 to which referencepotentials are supplied are formed in the wiring layers L2, and wiringsRL electrically connected to the pads PD1 are formed in the wiringlayers L2. Subsequently, as shown in FIG. 22C, the ground patterns GP3to which the reference potential is supplied are formed in the wiringlayers L3, and the wiring WL2 electrically connected to the wiring linesRL is formed in the wiring layers L3. Further, as shown in FIG. 22D, aground pattern GP4 to which a reference potential is supplied is formedin the wiring layer L4, and a wiring WL1 electrically connected to thewiring WL2 and a wiring 100 a connected to the wiring WL1 are formed inthe wiring layer L4 so as to be separated from the ground pattern GP4.

As described above, in the semiconductor device including the wiringsubstrate having the front surface and the back surface, the wiringsubstrate includes the pad PD1 formed on the back surface, the solderball SB connected to the pad PD1 and serving as an external connectionterminal located below the pad PD1, the wiring WL2 electricallyconnected to the pad PD1 and located above the pad PD, and the wiring100 a electrically connected to the wiring WL2. At this time, the widthof the wiring WL2 is larger than the width of the wiring 100 a.

In particular, the wiring substrate has a multi wiring structure, thepads PD1 are formed in the wiring layer L1, the wiring WL2 is formed inthe wiring layer L3 which is two layers higher than the wiring layer L1,and the wiring 100 a is formed in the wiring layer L4 which is one layerhigher than the wiring layer L3. The pad PD1 and the wiring WL2 areconnected to each other via a wiring (relay wiring) RL formed in thewiring layer L2 located one layer above the wiring layer L1 and onelayer below the wiring layer L3, a first via portion connecting the padPD1 and the wiring RL, and a second via portion connecting the wiring RLand the wiring WL2. Further, the wiring WL2 and the wiring 100 a areconnected to each other via a third via portion.

Here, as shown in FIG. 20, a wiring WL1 is interposed between the wiring100 a and the wiring WL2, and the width of the wiring 100 a is smallerthan the width of the wiring WL1, and the width of the wiring WL1 issmaller than the width of the wiring WL2. In other words, when it isconsidered that the wiring 100 a and the wiring WL1 are integrallyformed, the wiring 100 a includes a narrow portion having a first widthand a wide portion having a second width larger than the first width,which corresponds to the wiring WL1, and the wide portion can be said tobe provided between the narrow portion and the wiring WL2. At this time,for example, as shown in FIG. 20, the wide portion includes a portionwhose width increases from the narrow portion toward the interconnectionWL2.

Technical Features in Embodiment

Next, characteristic points in present embodiment will be described.

First, as shown in FIG. 20, for example, the first characteristic pointof the present embodiment is that the length and the widths of theinterconnection WL2 constituting the high-impedance delay section areadjusted. That is, the first characteristic point of the presentembodiment is that the concept of adjusting the phase and the concept ofintentionally shifting the characteristic impedances from 50Ω arecombined by adjusting the length and the width of the interconnectionWL2. More specifically, in present embodiment, as shown in FIG. 20, thelength of the wiring WL2 is increased so that the width of the wiringWL2 is larger than the width of the wiring 100 a and the angle(rotational angle) θ1 formed by the virtual line VL1 and the virtualline VL2 is 180 degrees or more. As a result, the phase can be adjustedso that the reflected waves at the input end and the output end arereduced. At this time, it is also required to consider adjusting thelength and width of the interconnection WL2 so that the characteristicimpedance of the connecting portion (low impedance delay portion+highimpedance delay portion) can be intentionally shifted from 50Ω. This isbecause, by combining the idea of phase adjustment and the idea ofintentionally shifting the characteristic impedance from 50Ω,high-frequency noise having a higher frequency than the impedance polecan be effectively removed while improving the signal transmissioncharacteristic in a frequency band lower than the impedance pole.

This point will be described below.

Present embodiment uses, for example, a wire WL2 constituting ahigh-impedance delay unit as a way of adjusting the phase of ahigh-frequency signal incident on the input end and the phase of areflected signal reflected at the output end and returned to the inputend again to 180 degrees after the high-frequency signal enters from theinput end. This is because, when the parasitic inductance of the wiringWL2 is set to “L” and the parasitic capacitance of the wiring WL2 is setto “C”, the phase difference between the input end and the output endcan be expressed by √(LC), and therefore, by adjusting the parasiticinductance and the parasitic capacitance of the wiring WL2, the phasedifference between the input end and the output end can be set to 90degrees to reduce reflected waves.

Specifically, first, as shown in FIG. 20, the width of the wiring WL2 ismade larger than the width of the wiring 100 a (“Configuration A”).Since the parasitic capacitances of the interconnection WL2 areincreased, it is possible to increase √(LC) indicating the phasedifferences. Further, as shown in FIG. 20, the length of theinterconnection WL2 is lengthened so that the angle (rotational angle)θ1 formed by the virtual line VL1 and the virtual line VL2 becomes 180degrees or more (“Configuration B”). As a result, since the parasiticinductances of the interconnection WL2 become large, it is possible toincrease √(LC) indicating the phase differences. As described above, byemploying the “configuration A” and the “configuration B”, it ispossible to synergistically increase √(LC) indicating the phasedifference, and as a result, it is possible to perform phase adjustmentfor reducing the reflected wave by setting the phase difference betweenthe input end and the output end to 90 degrees. In particular, thecombination of “configuration A” and “configuration B” is useful fromthe viewpoint of adjusting √(LC) indicating the phase difference. Thisis because, for example, it is difficult to realize the configuration ofthe wiring WL2 in which the phase difference between the input end andthe output end is 90 degrees only by the “configuration A”, and it isdifficult to realize the configuration of the wiring WL2 in which thephase difference between the input end and the output end is 90 degreesonly by the “configuration B”. That is, by the synergistic effects ofcombining the “configuration A” and the “configuration B”, theconfiguration of the interconnection WL2 in which the phase differencebetween the input end and the output end is 90 degrees can be easilyrealized.

In this manner, according to the first characteristic point in thepresent embodiment, the basic idea in the present embodiment can beembodied. That is, according to the first characteristic point of thepresent embodiment, by devising the layout pattern of the high-impedancedelay unit provided in the connection portion between the mountingsubstrate and the semiconductor device, the connection portion canfunction as the band-limiting filter. As a result, according to thefirst characteristic point of the present embodiment, it is possible toreduce high-frequency noises while improving the signal transmissioncharacteristics.

Hereinafter, a result of supporting that the first characteristic pointin the present embodiment can reduce high-frequency noises whileimproving the signal transmission performance will be described.

FIG. 23 is a graph showing the result of comparing the connectionstructure of the countermeasure shown in FIG. 11 with the connectionstructure in the present embodiment shown in FIG. 20 with respect to thefrequency dependence of the reflection loss and the frequency dependenceof the insertion loss. In FIG. 23, the dotted line is a graphcorresponding to the connection structure of the countermeasureproposal, and the solid line is a graph corresponding to the connectionstructure of the present embodiment. In FIG. 23, the horizontal axisrepresents the frequency. On the other hand, in FIG. 23, the verticalaxis on the left side indicates the reflection loss, and the verticalaxis on the right side indicates the insertion loss.

First, in FIG. 23, the dotted line showing the graph corresponding tothe connection structure of the countermeasure proposal shows that theinsertion loss is small even in the frequency band higher than thefrequency of 28 GHz which is twice the Nyquist frequency. This meansthat, in the connecting structures of the proposed countermeasures, notonly signals having a frequency lower than twice the Nyquist frequency(28 GHz) but also high-frequency noise having a frequency higher thantwice the Nyquist frequency (28 GHz) are passed well, therebydeteriorating the noise tolerance of the semiconductor device.

On the other hand, in FIG. 23, it can be seen that in the solid lineshowing graphs corresponding to the present embodiment connectingstructures, the insertion loss can be reduced in a frequency band lowerthan the frequency (28 GHz) twice the Nyquist frequency, while in afrequency band higher than the frequency (28 GHz) twice the Nyquistfrequency, the insertion loss is larger than in the countermeasureproposal. This means that, in present embodiment connects, signals lowerthan twice the Nyquist frequency (28 GHz) pass well, while highfrequency noises higher than twice the Nyquist frequency (28 GHz) can beblocked. As a result, it can be seen that the connecting structures inthe present embodiment function as a band-limiting filter and can reducehigh-frequency noises while improving the signal transmissionperformance. Thus, according to the present embodiment, it can be seenthat the performance of the semiconductor device can be improved ascompared with the countermeasure proposal.

As shown in FIG. 12, for example, the connecting structure in presentembodiment is a two-stage L/C ladder structure composed of a lowimpedance delay portion 10 and a high impedance delay portion 20, andthe number of impedance poles is one. However, the number of impedancepoles can be increased by increasing the number of stages of the L/Cladder structure. For example, when the frequency of the high-frequencynoise is high and the cutoff frequency for cutting off thehigh-frequency noise is set to a higher frequency, it is considered thatthe L/C ladder structure having one impedance pole and two stages isinsufficient. In this instance, for example, an additionalhigh-impedance delay section is added to the mounting substrate, or anadditional low-impedance delay section is inserted between thehigh-impedance delay section 20 and the wiring of the wiring substrate,i.e., a transmission line having a characteristic impedance of 50Ω,thereby increasing the cutoff frequency for cutting off high-frequencynoises.

Next, the second characteristic point of present embodiment is, forexample, as shown in FIG. 20, that a wiring WL1 having a width largerthan that of the wiring 100 a and a width smaller than that of thewiring WL2 is provided between the wiring 100 a and the wiring WL2. As aresult, discontinuities in the characteristic impedances at theboundaries between the wiring 100 a having a small width and the wiringWL2 having a large width can be alleviated. That is, in presentembodiment, the phase is adjusted by increasing the width of the wiringWL2 constituting the high impedance delay section 20, but in thisinstance, discontinuities in the characteristic impedance at the borderbetween the wiring 100 a having a small width and the wiring WL2 havinga large width become apparent, and there is a fear that the reflectionloss becomes large and the reflection loss becomes difficult to design.In this regard, by employing the second characteristic point in thepresent embodiment, the discontinuities in the characteristic impedancesare alleviated, and as a result, it is possible to suppress that thereflection loss becomes large and the design becomes difficult. Inparticular, from the viewpoint of alleviating discontinuities in thecharacteristic impedances at the boundaries between the wiring 100 ahaving a small width and the wiring WL2 having a large width whileemploying the first characteristic point in the present embodiment, itis desirable that the planar shape of the wiring WL1 has a shape inwhich the width gradually increases from the wiring 100 a side towardthe wiring WL2 side. In this instance, discontinuities in thecharacteristic impedances at the boundaries between the wiring 100 ahaving a small width and the wiring WL2 having a large width can besufficiently reduced.

Next, the third characteristic point of the present embodiment is that,for example, as shown in FIG. 20, the interconnection WL2 constitutingthe high-impedance delay portion is formed along the circumference ofthe circular pad PD1 in plan view. Thus, according to the presentembodiment, the semiconductor device can be designed independentlyregardless of the design of the mounting substrate.

The reason for this will be described below.

In FIG. 20, the wiring 200 a formed on the mounting substrate and thepad PD1 are connected by a solder ball (not shown in FIG. 20), and thecurrent flowing through the wiring 200 a flows in the pad PD1 along theheight direction (perpendicular direction) of the solder ball. Thismeans that the magnetic field generated due to the current flowingthrough the solder ball is generated along the circumferentialdirections of the pads PD1, as shown in FIG. 20, according to Ampere'slaw. At this time, since the wiring WL2 constituting the high-impedancedelay portion is arranged along the circumferential directions of thepads PD1, the wiring WL2 is arranged in parallel with the magnetic fieldgenerated by the current flowing through the solder balls. As a result,the high-impedance delay portion (wiring WL2) formed in the wiringsubstrate of the semiconductor device can eliminate mutual inductancesdue to interferences with currents flowing directly below (solderingballs). This means that the band-limiting filter by the high-impedancedelay portion (wiring WL2) formed in the wiring substrate can be made tofunction without being affected by the design of the mounting substrate.In other words, according to the third characteristic point of thepresent embodiment, even when a semiconductor device is mounted onvarious mounting substrate differing in design, the band-limiting filterformed in the semiconductor device can be made to function withoutchanging the design of the wiring substrate side of the semiconductordevice. As a result, according to the third characteristic point of thepresent embodiment, it is possible to achieve both the improvement ofthe signal transmission performance and the reduction of thehigh-frequency noise while ensuring the versatility of the semiconductordevice.

Modified Example 1

Next, first modified example will be described.

FIG. 24 is a diagram showing a connecting portion between the mountingsubstrate and the semiconductor device in the present first modifiedexample.

In FIG. 24, a wiring 100 a and a wiring 100 b are wirings formed on thesemiconductor device wiring substrate, and constitute a differentialwiring. On the other hand, the wirings 200 a and 200 b are wiringsformed in the mounting substrate, and constitute differential wirings.

As shown in FIG. 24, the wiring 100 a and the wiring 200 a are connectedby a connecting portion between the mounting substrate and thesemiconductor device. Specifically, the connecting portion includes awiring WL1 connected to the wiring 100 a, a wiring WL2 connected to thewiring WL1, and pads PD1 connected to the wiring WL2. Here, also in thepresent first modified example, the width of the wiring WL1 is largerthan the width of the wiring 100 a, and the width of the wiring WL2 islarger than the width of the wiring WL1. That is, the relationship ofthe width of the wiring 100 a<the width of the wiring WL1<the width ofthe wiring WL2 is established.

FIG. 25 is a cross-sectional view cut along the line A-A in FIG. 24.

In FIG. 25, a wiring 200 a is formed on the surface of the mountingsubstrate MB, and a solder ball SB, which is an external connectionterminal, is mounted on the wiring 200 a. A pad PD1 is formed above thesolder ball SB. The pad PD1 is formed on the wiring substrate of thesemiconductor device, and the solder ball SB is disposed so as to besandwiched between the pad PD1 and the wiring 200 a formed on themounting substrate MB. As a result, the wiring substrate of thesemiconductor device and the mounting substrate MB are electricallyconnected to each other via the solder balls SB.

As shown in FIG. 25, three wiring layers are formed in the wiringsubstrate, and pads PD1 connected to the solder balls SB are formed inthe lowermost wiring layer L1. The planar shape of the padding PD1includes a circular shape. As shown in FIG. 25, the pad PD1 is connectedwith the wiring WL2 formed in the wiring layer L2 located above thewiring layer L1 by way of a via portion. As shown in FIG. 24, theinterconnection WL2 is disposed so as to overlap with the pads PD1 inplan view. In plan view, the interconnection WL2 extends along thecircumference of the pads PD1. In particular, in FIG. 24, the wiring WL2has one end portion and the other end portion, and the angle θ2 formedby the imaginary line VL1 connecting the center point of the pad PD1 andthe one end portion of the wiring WL2 and the imaginary line VL2connecting the center point of the pad PD1 and the other end portion ofthe wiring WL2 is 180 degrees or more. As shown in FIG. 25, the wiringWL2 formed in the wiring layer L2 is connected to the wiring WL1 formedin the wiring layer L3 above the wiring layer L2 through a via portion.The wiring WL1 formed in the wiring layer L3 is connected to the wiring100 a formed in the same wiring layer L3. In this manner, the wiring 100a formed in the wiring substrate and the wiring 200 formed in themounting substrate MB are electrically connected to each other via theconnecting portion between the wiring substrate and the mountingsubstrate MB.

Here, the difference between the connection portion in the present firstmodified example shown in FIG. 25 and the connection portion in theembodiment shown in FIG. 21 is that, in the embodiment shown in FIG. 21,the multilayer wiring layer formed in the wiring substrate is formed offour layers (wiring layer L1 to wiring layer L4), whereas in the presentfirst modified example shown in FIG. 25, the multilayer wiring layerformed in the wiring substrate is formed of three layers (wiring layerL1 to wiring layer L3). In particular, in the embodiment shown in FIG.21, the wiring WL2 constituting the high-impedance delay portion isformed in the wiring layer L3, and this wiring WL2 is electricallyconnected to the pad PD1 formed in the wiring layer L1 under the wiringlayer L2 via the wiring RL formed in the wiring layer L2 under thewiring layer L3. In contrast, in the present first modified exampleshown in FIG. 25, the wiring WL2 constituting the high-impedance delayportion is formed in the wiring layer L2, and the wiring WL2 iselectrically connected to the pads PD1 formed in the wiring layer L1below the wiring layer L2. That is, in the embodiment shown in FIG. 21,the wiring RL is interposed between the wiring WL2 and the pad PD1 inthe thickness direction of the wiring substrate, whereas in the presentfirst modified example shown in FIG. 25, the wiring RL is not interposedbetween the wiring WL2 and the pad PD1 in the thickness direction of thewiring substrate. As a result, in the present modified example,distances between the wires WL2 and the pads PD1 are smaller than thosein the embodiment. This means that the mutual inductances between theinterconnection WL2 and the pads PD1 are larger in the present modifiedexample than in the embodiment. As a result, in the present firstmodified example, since the parasitic inductance can be increasedwithout making the length of the interconnection WL2 constituting thehigh-impedance delay section longer than in the embodiment, the phasedifference between the input end and the output end can be adjusted to90 degrees. That is, as can be seen by comparing FIG. 20 and FIG. 24,the angle θ2 in the present first modified example can be made smallerthan the angle θ1 in the embodiment, but the phase difference betweenthe input end and the output end can be adjusted to 90 degrees.

FIGS. 26A and 26B are a plan view schematically showing a layout patternof each wiring layer constituting the multilayered wiring layer formedin the wiring substrate. In particular, FIG. 26A is a diagram showing alayout pattern of the wiring layer L1, and FIG. 26B is a diagram showinga layout pattern of the wiring layer L2. FIG. 22C is a diagram showing alayout pattern of the wiring layer L3.

As shown in FIG. 26A, a pad PD1 to which a signal potential (signalvoltage) is applied is formed in the interconnection layer L1, and aground pattern GP1 to which a reference potential (ground voltage) issupplied is formed so as to surround the pad PD1 at a distance from theinterconnection layer L1. A solder ball connecting the ground patternGP1 and the mounting substrate is placed at a position indicated by abroken line.

Next, as shown in FIG. 22B, a ground pattern GP2 to which a referencepotential is supplied is formed in the wiring layer L2, and a wiring WL2electrically connected to the pads PD1 is formed in the wiring layer L2.Subsequently, as shown in FIG. 22C, a ground pattern GP3 to which areference potential is supplied is formed in the wiring layer L3, and awiring WL1 electrically connected to the wiring WL2 and a wiring 100 aconnected to the wiring WL1 are formed in the wiring layer L3 so as tobe separated from the ground pattern GP3.

Hereinafter, the results of the present first modified example will bedescribed to confirm that high-frequency noises can be reduced whileimproving the signal transmission performance.

FIG. 27 is a graph showing the result of comparing the connectionstructure of the countermeasure shown in FIG. 11 and the connectionstructure in the present first modified example shown in FIG. 24 withrespect to the frequency dependence of the reflection loss and thefrequency dependence of the insertion loss. In FIG. 27, the dotted lineis a graph corresponding to the connection structure of thecountermeasure proposal, and the solid line is a graph corresponding tothe connection structure of the present first modified example. In FIG.27, the horizontal axis represents the frequency. On the other hand, inFIG. 27, the vertical axis on the left side indicates the reflectionloss, and the vertical axis on the right side indicates the insertionloss.

First, in FIG. 27, the dotted line showing the graph corresponding tothe connection structure of the countermeasure proposal shows that theinsertion loss is small even in the frequency band higher than thefrequency of 28 GHz which is twice the Nyquist frequency. This meansthat, in the connecting structures of the proposed countermeasures, notonly signals having a frequency lower than twice the Nyquist frequency(28 GHz) but also high-frequency noise having a frequency higher thantwice the Nyquist frequency (28 GHz) are passed well, therebydeteriorating the noise tolerance of the semiconductor device.

On the other hand, in FIG. 27, it can be seen from the solid lineshowing graphs corresponding to the connecting structures of the presentfirst modified example that the insertion loss can be reduced in thefrequency band lower than the frequency (28 GHz) twice the Nyquistfrequency, while the insertion loss is remarkably increased in thefrequency band higher than the frequency (28 GHz) twice the Nyquistfrequency as compared with the countermeasure proposal. This means thatin the interconnect of the present first modified example, signals lowerthan twice the Nyquist frequency (28 GHz) pass well, while highfrequency noises higher than twice the Nyquist frequency (28 GHz) can beblocked. As a result, it can be seen that the connecting structures ofthe present first modified example can function as a band-limitingfilter, and can reduce high-frequency noises while improving the signaltransmission performance. As a result, according to the present firstmodified example, it is possible to improve the performance of thesemiconductor device as compared with the countermeasure proposal.

Furthermore, when comparing the graph (solid line) corresponding to theconnection structure of the present first modified example shown in FIG.27 with the graph (solid line) corresponding to the connection structureof the embodiment shown in FIG. 23, it can be seen that the insertionloss of the present first modified example is remarkably larger than theinsertion loss of the present embodiment at a frequency higher than afrequency (28 GHz) twice as high as the Nyquist frequency. This meansthat the first modified example has a higher cutoff performance againsthigh-frequency noises than the embodiment at a frequency twice as highas the Nyquist frequency (28 GHz). As described above, the connectionstructure of the present first modified example realizes theband-limiting filter of higher performance than the connection structureof the embodiment, and it is understood that high-frequency noises canbe reduced while improving the signal transmission performance in thepresent first modified example.

Next, in the connection structure of the present first modified exampleand the connection structure of the countermeasure proposal, the resultsof comparing the resistance to high-frequency noises by simulations willbe described.

In the simulations, for example, sinusoidal high-frequency noises areinjected from the signal-input-pin positions of the semiconductordevice. This high-frequency noise is synthesized into a high-frequencysignal (56 Gbps/PAM4 signal) transmitted from the transmitter to thesemiconductor device, and the synthesized high-frequency noise isinputted to the semiconductor device. After that, the high-frequencysignal on which the high-frequency noise is superimposed reaches thereceiving unit, and thereafter, the waveform is shaped by, for example,an equalizer. The received waveforms after the waveform shaping arecompared.

At this time, if the frequency of the high-frequency noise, which is asine wave, is a rational multiple (in particular, an integer multiple)of the Nyquist frequency of the high-frequency signal, the influence ofthe high-frequency noise does not appear, so that the frequency of thehigh-frequency noise to be added is an irrational multiple of theNyquist frequency of the high-frequency signal.

FIGS. 28A and 28B are a graph showing the frequency dependence of theheight and width of the eye pattern in the case where the insertion lossis 1 dB or less and the insertion loss is about twice the Nyquistfrequency of the high-frequency signal.

In particular, FIG. 28A is a graph showing the frequency dependence ofthe height of the eye pattern, and FIG. 28B is a graph showing thefrequency dependence of the width of the eye pattern.

First, in FIG. 28A and FIG. 28B, the dotted line is a graphcorresponding to the connection structure of the countermeasureproposal, and the solid line is a graph corresponding to the connectionstructure of the present first modified example.

As shown in FIG. 28A and FIG. 28B, when high-frequency noises areinjected, the eye pattern is completely closed in the countermeasureplan shown by the dotted line, whereas the eye pattern is not muchchanged in the present first modified example shown by the solid line.In other words, this first modified example is less susceptible tohigh-frequency noise and is highly resistant to high-frequency noise.

Specifically, FIG. 29A is a diagram showing the eye pattern in thecountermeasure plan in the case where there is no high-frequency noise,and FIG. 29B is a diagram showing the eye pattern in the present firstmodified example in the case where there is no high-frequency noise. Onthe other hand, FIG. 30A is a diagram showing the eye pattern in thecountermeasure proposal when there is high-frequency noise, and FIG. 30Bis a diagram showing the eye pattern in the present first modifiedexample when there is high-frequency noise.

As shown in FIG. 29A and FIG. 29B, it can be seen that the receptionwaveforms when no high-frequency noises are added are substantially thesame in the countermeasure proposal and the present first modifiedexample. On the other hand, as shown in FIGS. 30A and 30B, whenhigh-frequency noises are injected, clear differences appear between thecountermeasure proposal and the present first modified example withrespect to the eye pattern. That is, it can be seen that the receptionwaveform (FIG. 30A) corresponding to the connection structure of thecountermeasure proposal is equivalent to the reception waveform (FIG.29B) when high-frequency noises are not added to the eye pattern in thereception waveform (FIG. 30B) corresponding to the connection structureof the present first modified example, while the eye pattern iscollapsed in the reception waveform (FIG. 30A) corresponding to theconnection structure of the countermeasure proposal. That is, when theconnecting structures of the present first modified example areemployed, it is understood that the received waveforms are notsubstantially affected by high-frequency noises.

Next, FIGS. 31A and 31B are a graph showing the frequency dependence ofthe height and width of the eye pattern in the case where the insertionloss is 1 dB or less and the pad pitch is 1.0 mm in the case where theinsertion loss is about 1.5 times the Nyquist frequency of thehigh-frequency signal.

In particular, FIG. 31A is a graph showing the frequency dependence ofthe height of the eye pattern, and FIG. 31B is a graph showing thefrequency dependence of the width of the eye pattern.

First, in FIG. 31A and FIG. 31B, the dotted line is a graphcorresponding to the connection structure of the countermeasureproposal, and the solid line is a graph corresponding to the connectionstructure of the present first modified example.

As shown in FIG. 31A and FIG. 31B, when high-frequency noises areinjected, the eye pattern is completely closed in the countermeasureplan shown by the dotted line, whereas the eye pattern is not muchchanged in the present first modified example shown by the solid line.In other words, this first modified example is less susceptible tohigh-frequency noise and is highly resistant to high-frequency noise.

Specifically, FIG. 32A is a diagram showing the eye pattern in thecountermeasure proposal when there is no high-frequency noise, and FIG.32B is a diagram showing the eye pattern in the present first modifiedexample when there is no high-frequency noise. On the other hand, FIG.33A is a diagram showing the eye pattern in the countermeasure proposalwhen there is high-frequency noise, and FIG. 33B is a diagram showingthe eye pattern in the present first modified example when there ishigh-frequency noise.

As shown in FIG. 32A and FIG. 32B, the reception waveforms when nohigh-frequency noises are added are substantially the same in thecountermeasure proposal and the present first modified example, but itis understood that the eye pattern of the present first modified exampleis slightly smaller than the eye pattern of the countermeasure proposal.However, as shown in FIG. 33A and FIG. 33B, when high-frequency noisesare injected, this relationship is reversed, and further, it can be seenthat clear differences appear between the countermeasure proposal andthe present first modified example with respect to the eye pattern. Thatis, it can be seen that the reception waveform (FIG. 33A) correspondingto the connection structure of the countermeasure proposal completelycollapses the eye pattern, whereas the reception waveform (FIG. 33B)corresponding to the connection structure of the present first modifiedexample is equivalent to the reception waveform (FIG. 32B) when thehigh-frequency noises are not added to the eye pattern. That is, whenthe connecting structures of the present first modified example areemployed, the received waveforms are substantially not affected byhigh-frequency noises.

Next, FIGS. 34A and 33B are a graph showing the frequency dependence ofthe height and width of the eye pattern in the case where the insertionloss is 1 dB or less and the pad pitch is 0.8 mm in the case where theband is about 1.5 times the Nyquist frequency of the high-frequencysignal.

In particular, FIG. 34A is a graph showing the frequency dependence ofthe height of the eye pattern, and FIG. 34B is a graph showing thefrequency dependence of the width of the eye pattern.

First, in FIG. 34A and FIG. 34B, the dotted line is a graphcorresponding to the connection structure of the countermeasureproposal, and the solid line is a graph corresponding to the connectionstructure of the present first modified example.

As shown in FIG. 34A and FIG. 34B, when high-frequency noises areinjected, the eye pattern is completely closed in the countermeasureplan shown by the dotted line, whereas the eye pattern is not muchchanged in the present first modified example shown by the solid line.In other words, this first modified example is less susceptible tohigh-frequency noise and is highly resistant to high-frequency noise.

Specifically, FIG. 35A is a diagram showing the eye pattern in thecountermeasure plan in the case where there is no high-frequency noise,and FIG. 35B is a diagram showing the eye pattern in the present firstmodified example in the case where there is no high-frequency noise. Onthe other hand, FIG. 36A is a diagram showing the eye pattern in thecountermeasure proposal when there is high-frequency noise, and FIG. 36Bis a diagram showing the eye pattern in the present first modifiedexample when there is high-frequency noise.

As shown in FIG. 35A and FIG. 35B, the reception waveforms when nohigh-frequency noises are added are substantially the same in thecountermeasure proposal and the present first modified example, but itis understood that the eye pattern of the present first modified exampleis slightly smaller than the eye pattern of the countermeasure proposal.However, as shown in FIG. 36A and FIG. 36B, when high-frequency noisesare injected, this relationship is reversed, and moreover, cleardifferences appear between the countermeasure proposal and the presentfirst modified example with respect to the eye patterns. That is, it canbe seen that the reception waveform (FIG. 36A) corresponding to theconnection structure of the countermeasure proposal completely collapsesthe eye pattern, whereas the reception waveform (FIG. 36B) correspondingto the connection structure of the present first modified example isequivalent to the reception waveform (FIG. 35B) when high-frequencynoises are not added. That is, when the connecting structures of thepresent first modified example are employed, the received waveforms aresubstantially not affected by high-frequency noises.

As described above, according to the present first modified example, itis possible to make the received waveforms less susceptible tohigh-frequency noises. In other words, according to the present firstmodified example, it is possible to increase the immunity tohigh-frequency noises.

Modified Example 2

In the embodiment, the electromagnetic wave absorption pattern forabsorbing the scattered electromagnetic wave is not provided above thepad, but the electromagnetic wave absorption pattern for absorbing thescattered electromagnetic wave may be provided above the pad. That is,since the basic idea of the embodiment is to intentionally limit thesignal transmission band, the configuration of providing theelectromagnetic wave absorption pattern is not indispensable, but if theconfiguration of providing the electromagnetic wave absorption patternabove the pad is adopted, the frequency response in the vicinity of theimpedance pole can be easily controlled. By providing theelectromagnetic wave absorption pattern, it is possible to absorb thereflected wave, thereby making the impedance pole broader. That is, thefact that the impedance pole can be made broader means that thefrequency dependence of the insertion loss can be flattened in thefrequency band on the low frequency side of the impedance pole, therebyimproving the signal transmission characteristic in the frequency bandon the low frequency side of the impedance pole.

The electromagnetic wave absorption pattern can be composed of, forexample, a mesh pattern.

Modified Example 3

FIG. 37 is a schematic diagram showing a connecting configuration in thepresent third modified example.

As shown in FIG. 37, a via portion between the interconnect WL2 and thepad PD1 constituting the high-impedance portion may be provided at aposition not overlapping with the pad PD1 in plan view. If the length ofthe wiring WL2 is maintained, the electric length (phase) decreases, andtherefore, for example, as shown in FIG. 37, the extension portion EXUneeds to be provided in the wiring WL2 in order to increase theparasitic inductance.

Modified Example 4

FIG. 38 is a schematic diagram showing a connecting configuration in thepresent fourth modified example.

As shown in FIG. 38, a ground pattern 300 a that covers the pad PD1 in aplanar manner may be provided above the pad PD1. Since the parasiticcapacitances can be increased, the degree of flexibility in designingthe high-impedance delay section (interconnection WL2) can be improved.However, the ground pattern provided above the pads PD1 does not have tobe shaped like the ground pattern 300 a, and for example, as shown inFIG. 39, the ground pattern 300 b may be formed of a wide patterncovering the interconnection WL2 constituting the high-impedanceportion. In this instance, both the parasitic capacitances and theparasitic inductances of the interconnection WL2 constituting thehigh-impedance delay section can be precisely adjusted.

Modified Example 5

In the embodiment, the basic idea in the embodiment has been describedby taking a design for 56 Gbps per PAM4 transmission as an example, butthe basic idea in the embodiment can also be applied to a design fortransmission in a higher frequency band (112 Gbps per PAM4), forexample.

Specifically, FIG. 40 is a graph showing the frequency dependence of thereflection loss and the frequency dependence of the insertion loss in atransmission design example (pad pitch: 1 mm) of 112 Gbps per PAM4. FIG.41 is a graph showing the frequency dependence of the reflection lossand the frequency dependence of the insertion loss in a transmissiondesign example (pad pitch: 0.8 mm) of 112 Gbps per PAM4.

As shown in FIGS. 40 and 41, by adopting the basic idea of theembodiment, it is possible to design a band-limiting filter capable ofpassing a signal lower than 50 GHz well, while blocking a high-frequencynoise higher than 50 GHz.

The invention made by the present inventor has been described above indetail based on the embodiment, but the present invention is not limitedto the embodiment described above, and it is needless to say thatvarious modifications can be made without departing from the gistthereof.

The embodiment includes the following modes.

(Appendix 1) (Basic Concept)

A semiconductor device comprising:

a first wiring; and

an impedance change portion connected with the first wiring,

wherein the impedance change portion has:

a high impedance delay portion having a characteristics impedance higherthan a characteristics impedance of the first wiring; and

a low impedance delay portion having a characteristics impedance lowerthan a characteristics impedance of the first wiring,

wherein, in the frequency dependence of a reflection loss between thefirst wiring and the impedance change portion, there is an impedancepole indicating a frequency at which the reflection loss is minimized,and

wherein a characteristics impedance of the impedance change portion seenfrom the first wiring is sifted from the characteristics impedance ofthe first wiring.

(Appendix 2)

The semiconductor device according to the appendix 1, wherein theimpedance change portion is served as a band-limiting filter.

(Appendix 3)

The semiconductor device according to the appendix 1,

wherein the high impedance delay portion has a second wiring, and

wherein the impedance pole is formed by adjusting each of a length ofthe second wiring and a width of the second wiring.

(Appendix 4) (Basic Concept)

An electronic device comprising:

a mother board; and

a semiconductor device mounted on the mother board,

wherein the mother board has a transmission line electrically connectedwith the semiconductor device,

wherein the semiconductor device has an impedance change portion,

wherein the impedance change portion has:

a high impedance delay portion having a characteristics impedance higherthan a characteristics impedance of the transmission line; and

a low impedance delay portion having a characteristics impedance lowerthan a characteristics impedance of the transmission line,

wherein, in the frequency dependence of a reflection loss between thetransmission line and the impedance change portion, there is animpedance pole indicating a frequency at which the reflection loss isminimized, and

wherein a characteristics impedance of the impedance change portion seenfrom the transmission line is sifted from the characteristics impedanceof the transmission line.

(Appendix 5)

The electronic device according to the appendix 4, wherein the impedancechange portion is served as a band-limiting filter.

(Appendix 6)

The electronic device according to the appendix 4,

wherein the high impedance delay portion has a wiring, and

wherein the impedance pole is formed by adjusting each of a length ofthe wiring and a width of the wiring.

What is claimed is:
 1. A semiconductor device comprising: a wiringsubstrate having a front surface and a back surface, wherein the wiringsubstrate has: a pad formed on the back surface; an external connectionterminal connected to the pad, and located below the pad; a first wiringelectrically connected with the pad, and located above the pad; and asecond wiring electrically connected with the first wiring, wherein thefirst wiring has 1) a first length that is parallel to the back surfaceof the wiring substrate 2) a first width that is parallel to the backsurface of the wiring substrate and 3) a first height that isperpendicular to the back surface of the wiring substrate, wherein thefirst width is shorter than the first length, wherein the second wiringhas 1) a second length that is parallel to the back surface of thewiring substrate 2) a second width that is parallel to the back surfaceof the wiring substrate and 3) a second height that is perpendicular tothe back surface of the wiring substrate, wherein the second width isshorter than the second length, and wherein the first width of the firstwiring is greater than the second width of the second wiring.
 2. Thesemiconductor device according to claim 1, wherein the wiring substratehas a multi wiring structure, wherein the pad is formed in a firstwiring layer, wherein the first wiring is formed in a second wiringlayer located one layer above than the first wiring layer, wherein thesecond wiring is formed in a third wiring layer located one layer abovethan the second wiring layer, wherein the pad and the first wiring areconnected with each other by way of a first via portion, and wherein thefirst wiring and the second wiring are connected with each other by wayof a second via portion.
 3. The semiconductor device according to claim1, wherein the wiring substrate has a multi wiring structure, whereinthe pad is formed in a first wiring layer, wherein the first wiring isformed in a third wiring layer located two layers above than the firstwiring layer, wherein the second wiring is formed in a fourth wiringlayer located one layer above than the third wiring layer, wherein thepad and the first wiring are connected with each other by way of: arelay wiring formed in a second wiring layer that is located one layerabove than the first wiring layer, and that is located one layer belowthan the third wiring layer, a first via portion connected the pad withthe relay wiring, and a second via portion connected the relay wiringwith the first wiring, and wherein the first wiring and the secondwiring are connected with each other by way of a third via portion. 4.The semiconductor device according to claim 1, wherein the second wiringhas: a narrow portion having a first width; and a wide portion having asecond width greater than the first width, and wherein the wide portionis situated between the narrow portion and the first wiring.
 5. Thesemiconductor device according to claim 4, wherein the wide portion hasa portion that increases in width from the narrow portion toward thefirst wiring.
 6. The semiconductor device according to claim 1, whereinthe first wiring has a portion overlapping with the pad in a plan view.7. The semiconductor device according to claim 6, wherein a planar shapeof the pad is a circular shape, and wherein, in the plan view, the firstwiring is extended along an edge of the pad.
 8. The semiconductor deviceaccording to claim 7, wherein the pad and the first wiring are connectedwith each other by way of a first via portion, wherein the first wiringand the second wiring are connected with each other by way of a secondvia portion, wherein the first wiring has 1) a first end portion that isin contact with the first via portion and 2) a second end portion thatis in contact with the second via portion, wherein the first wiringextends for an arc length of an angle of 180 degrees or more about acenter point of the pad, wherein the first length of the first wiring isequivalent to the arc length, and wherein the angle is an angle formedbetween 1) a first virtual line that connects the center point of thepad and the first end portion of the first wiring and 2) a secondvirtual line that connects the center point of the pad and the secondend portion of the first wiring.
 9. The semiconductor device accordingto claim 8, wherein the angle formed by the first virtual line and thesecond virtual line is 220 degrees or more, and 340 degrees or less. 10.The semiconductor device according to claim 1, wherein anelectromagnetic wave absorption pattern is situated above the firstwiring.
 11. The semiconductor device according to claim 10, wherein theelectromagnetic wave absorption pattern is formed in mesh shape.
 12. Thesemiconductor device according to claim 1, wherein each of the firstwiring and the second wiring is a wiring for signal, and wherein the padis a pad for signal.
 13. The semiconductor device according to claim 12,wherein the wiring for signal is a wiring for transmitting a four-valuedsignal.
 14. The semiconductor device according to claim 1, wherein aground pattern is situated above the first wiring.
 15. The semiconductordevice according to claim 14, wherein the first wiring has a portionoverlapping with the ground pattern in a plan view.